Hardware Restriction Analysis

This section explores how physical hardware constraints—specifically code scaling and qubit connectivity—impact the effectiveness of QEC codes.

1. The Overhead of Increasing Code Distance

Contrary to theoretical expectations, increasing code distance does not consistently improve logical performance on realistic hardware. On average, raising the distance (e.g., from 3 to 5) actually raises logical error rates by approximately 0.012 due to the overhead of additional qubits and gates.

Distance Scaling Overhead

Figure 1: Scaling of logical error rate with increased code distance on constrained topologies.

Takeaway #1: Increasing code distance does not consistently improve logical performance due to overhead. This suggests that once a code shows effectiveness, we should use available device scale to run larger protected circuits instead of just raising the distance.

2. The Dominance of Qubit Connectivity

Our experiments show that qubit connectivity is the most critical factor for QEC effectiveness. Transitioning from a 2D grid to an idealized fully connected layout reduces the logical error rate by 81.92% on average. In realistic mid-term devices, mechanisms like qubit shuttling (trapped-ion) improve performance by 45% compared to static constrained layouts.

Connectivity Impact

Figure 2: Impact of various topologies on logical error rates across different code families.

Takeaway #2: Connectivity is a crucial factor in the effectiveness of QEC. While fully connected topologies are currently physically unrealistic for superconducting qubits, realistic partial-connectivity mechanisms like shuttling are essential to unlock the full potential of QEC.